Unlimited Job Postings Subscription - $99/yr!

Job Details

Senior IC Layout Engineer

  2025-07-15     Lattice     all cities,ID  
Description:

Lattice Overview

There is energy here… energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, teams, results, and customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists, partnered with world-class sales, marketing, and support teams, developing programmable logic solutions that are changing the industry.

Our focus is on R&D, product innovation, and customer service. We bring total commitment and a keenly sharp competitive personality to these areas. If you thrive in a fast-paced, results-oriented environment, seek individual success within a "team first" organization, and believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may be just what you're looking for.

Responsibilities & Skills

Job Summary:

Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Analyze equipment to establish operation data, conduct experimental tests, and evaluate results. Review vendor capabilities to support development. Create high-quality analog, mixed-signal, and custom digital layouts. Require at least 5+ years of proven experience in custom and semi-custom layout of various IPs, including memory, array cells, analog, mixed-signal blocks, Serdes, and chip-level layout integration. Responsibilities include IP layout ownership, sector and FC physical integration support, and methodology improvement participation. Tasks include custom layout implementation of ECOs and LCOs, physical verification runs (e.g., DRC, LVS, ESD, DFM, Ant, PERC, EMIR), resolving technical issues, communicating with stakeholders, and task administration.

Accountabilities:

  • Own IP layout, manage resources, schedules, and sign-off documentation for Final Design Review.
  • Collaborate with circuit designers to understand and implement layout constraints.
  • Work with the EDA group to address CAD tool and flow issues.
  • Conduct layout quality reviews of cells, IP blocks, sector, and FC physical integration.
  • Consider device matching, noise, shielding, ESD, and latch-up in analog, mixed-signal, and digital circuits.
  • Run and analyze LPE, pre/post-layout simulations.

Required Skills:

  • Minimum 5 years of solid experience in Custom Layout Engineering.
  • Proficiency in custom layout of IP blocks up to full chip layout using Cadence Virtuoso and physical verification with Siemens Calibre.
  • Experience in analyzing and debugging EM-IR using Cadence Voltus.
  • Experience in generating LPE.
  • Automation skills (e.g., Cadence SKILL scripting) are a plus.
  • Familiarity with FinFET technology nodes is a plus.
  • P&R experience is a plus.
  • Ability to manage project team performance.

Lattice values its employees as its greatest asset. We strive to provide comprehensive compensation and benefits to attract, retain, motivate, reward, and celebrate top talent. As an international, service-driven developer of innovative low-cost, low-power programmable design solutions, our global workforce of approximately 800 shares a commitment to customer success and a relentless drive to win.

Learn more about our FPGA, CPLD, and programmable power management devices at www.latticesemi.com. Follow us on Twitter, Facebook, or RSS. We embrace diversity of individuals, ideas, perspectives, and insights, and welcome applications from all qualified candidates.

Feel the energy.

#J-18808-Ljbffr


Apply for this Job

Please use the APPLY HERE link below to view additional details and application instructions.

Apply Here

Back to Search