Job Details

Job Description

As a Lead Layout Engineer, you will be responsible for the top-level integration of analog and mixed-signal ICs. You will lead the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.

Key Responsibilities

• Lead the top-level layout integration of analog/mixed-signal chips (analog on top);
• Define and implement floorplanning and padframe design;
• Generate and integrate analog layouts at block and chip level;
• Perform pin placement, parasitic extraction, and layout optimization;
• Ensure compliance with DRC, LVS, and support tape-out activities;
• Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMV requirements.

Additional Information

What we offer:

• Pay for Performance: Achievement Bonuses and Rewards;
• Relocation Bonus for non-Timisoara Residents;
• Recommendation Bonuses for new team members;
• Flexibility Program including flexible hours, mobile work, and sabbaticals.

Wellbeing:

• Health & Wellness (Private Health Insurance, Life Insurance, Sport activities, etc.);
• Different discounts (glasses, tires, medical, shopping);
• In-house restaurant & coffee corners.

Life-Long Learning:

• Technical, Soft Skills & Leadership trainings;
• Dedicated Programs and Conferences;
• Free Language Courses (English, German, French, etc.);
• Access to e-learning platforms;
• Career development opportunities (local and international);
• Internal development communities (Experts, Agile Community of Practice, Artificial Intelligence, etc.).

Ready to take your career to the next level and join us at the start of something extraordinary? Apply now to become a part of AUMOVIO and drive the future of mobility together with us!

Qualifications

• Master of Science / PhD in Electrical Engineering / Microelectronics / Physics or similar;
• 5–10 years of experience in analog layout design;
• Proven experience in top-level layout integration;
• Strong expertise in BCD technologies (65nm to 180nm);
• Deep understanding of deep submicron effects (parasitics, coupling, matching);
• Proficient in layout tools for design, DRC, LVS, and extraction;
• Basic knowledge of analog circuit design.

Company Description